The present invention relates to methods for producing integrated circuit devices and more specifically to a method for planarizing integrated circuit devices using spin on glass (SOG) and chemical mechanical polish (CMP).
Planarization of integrated circuit devices is necessary and desirable to facilitate masking and etching operations. A planarized surface provides a constant depth of focus across the surface of a die for exposing patterns in a photolithography emulsion. While complete planarization is desirable, it is difficult to achieve as the topology of integrated circuit varies across the surface of a die on a wafer.
Planarization of metal interconnect layers improves the yield of devices off of a wafer and the reliability of such devices. Planarization allows the metal interconnect layer to be at a constant thickness across the circuit of a die. Planarization also minimizes the presence of cavities and allows metal interconnect lines to be continuous, where they would otherwise be discontinuous over a non-planar surface containing cavities.
Known methods for planarizing sub-micron device geometries include multiple silicon oxide depositions with insitu etches to fill the spaces between metal lines prior to CMP. This method is also used to fill cavities within the silicon, with an etch process being used to etch away oxide outside the cavities.
However, this method suffers from the disadvantages of high expense, low throughput, process complexity, high defect density, and the presence of material having a high dielectric constant between adjacent metal lines. For surfaces having aspect ratios (defined as the height of a feature divided by the distance to the closest feature) greater than about 1.6, this method fails.
Therefore, it would be desirable to provide a planarization process which does not suffer from the disadvantages of known planarization steps.